At FDU: Dr. Kalyan Mondal

Office: Room M116

1000 River Road
T-MU1-01
Teaneck, NJ 07666

Voice: (201) 692-2123

Dr. Kalyan Mondal

Assistant Professor of Electrical Engineering & Coordinator of Information Technology

Kalyan Mondal earned his Ph.D. in Electrical Engineering from the University of California, Santa Barbara and M.Tech. in Computer and System Sciences from the University of Kolkata, India. He has many years of industrial experience with Bell Laboratories, Murray Hill, NJ and prior teaching experience at Lehigh University, Bethlehem, PA.

Courses:
     EENG4375 - Energy Conversion Systems
     EENG3224 - Digital Signal Processing
     EENG6633 - Digital Signal Processing
     EENG7753 - Applications of Digital Signal Processing
     EENG7852 - DSP with C on DSP Processors
          (Using TMS320C6713 DSK)
     EENG7715 - Integrated Circuit Devices
     EENG7755 - VLSI Systems

Student Projects:
     * Embedded System Labs
          Spring 2009 (Dmitriy Kalantarov )
     * DSP Subsystem Implementation on VLSI
          Summer - Fall 2008 (Hemant Koka & Shivaram T.)
     * Wireless Link Studies using IEEE 802.11a, 802.16d PHY      SIMULINK Models - MS Thesis
          Spring 2007 - Summer 2008 (Pranesh Shah)
     * Comparative Studies on Media Acceess Controllers in      Ethernet & Wireless LAN
          Fall 2007 - Spring 2008 (Maoon Rashed)
     * VHDL Design of a Booth Encoded Parallel Multiplier on      Mentor Graphics VLSI Design System
          Fall 2006 (Rajeev Argula & Deepthi Nandigum)
     * Speech Coding Studies using a MATLAB ADPCM Model
          Fall 2006 (Dov Alperin)

Other Projects:
     * Decision Feedback Equalizer based upon Statistical Eye
     * Multi-stage Decimators for Sigma-Delta A/D Converters
     * Aperture Functions for Sparse Arrays in Ultrasound Scanners
     * Performance Characterization of Cooperative WiMAX Systems
     * PCI-Express to IEEE 1394b Host Controller IC Design
          2005-6 (Agere Systems)
     * AHB to RapidIO Bridge IP Development
          2003-4 (Agere Systems)
     * OC-48 Sonet Add Drop Multiplexer IC Design
          1999-2002 (Agere Systems)
     * DTV Baseband Demodulator IC Design
          1997-8 (Lucent Technologies)
     * Variable Baud Rate Cable Demodulator IC Design
          1995-6 (Lucent Technologies)
     * MPEG-2 Simple Profile Video Decoder IC Design
          1992-4 (AT&T Bell Laboratories)
     * Automated DSP VLSI Layout Generators
          1987-91 (AT&T Bell Laboratories)
     * 32-b Floating-Point DSP IC Design
          1983-5 (Bell Laboratories)

Recent Publications:
     • “General Polynomial Factorization-Based Design of Sparse Periodic Linear Arrays," to be submitted to IEEE Trans. on Ultrasonics, Ferroelectrics and Frequency Control, 2009.
     • "Constrained Statistical Decision Feedback Equalization," to be submitted to ICASSP2010.
     • "Design of Optimum Low Power Decimating Filters," submitted to IET Circuits, Devices & Systems, Aug. 2009.
     • “Fixed WiMAX Downlink Spectral Efficiency and Throughput Measurements under Channel Impairments", CSIE09, Los Angeles, April 2009.
     • “Design of Sparse Arrays with High Sidelobe Rejection”, 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, December 2008.
     • “Challenges in Teaching a Digital Signal Processing Course to International Graduate Students”, ASEE Mid-Atlantic Spring 2007 Conference, NJIT, April 2007.
     • “Channel Sequencing Using a Round-Robin Scheduler”, US Patent 6791991, September 2004.
     • "Adaptive Frequency Correction In A Wireless Communications System, Such As For GSM And IS54", US Patent 6522696, February 2003.
     • “Fixed clock based arbitrary symbol rate timing recovery loop”, US Patent 6,295,325, September 2001.
     • “Variable Baudrate QAM Demodulation Scheme”, US Patent 6,282,248, August 2001.
     • “Trellis Decoder for Real-Time Video Rate Decoding and Deinterleaving”, US Patent 6,094,739, July 2000.
     • “Amplitude based coarse automatic gain control circuit”, US Patent 6,081,565, June 2000.
     • “DVB Frame Synchronization”, US Patent 6,072,839, June 2000.
     • “A Digital Television Demodulator IC with 256 Tap Equalizer”, Invited Paper, Proc.1999 IEEE International Solid State Circuits Conference, p. 336, February 1999
     • “Equalizer Filter Configuration for Processing Real-Valued and Complex-Valued Signal Samples”, US Patent 5,912,828, June 1999.
     • “Digital Television System Architecture and Chip Set”, Invited Paper, CODEC 98, Calcutta, January 1998.
     • “HDTV/DTV – New Technologies”, Invited Talk in International Business Communications High Definition & Digital Television Seminar, Las Vegas, pp. 117-140, December 1997.

Links of interest:

Student Scholarships & College Search
DSP Technical Stuff, Jobs, etc.
Chip Design Made Easy

Email address: mondal@fdu.edu